Speed Key Name: buf
|
Signal name and type |
Description |
|
Digital input: <enable> |
Allows all digital inputs to propagate to the corresponding digital outputs for as long as the input is high. When the enable line is low, all outputs are set to logic low/0 and the inputs are ignored. When <enable> goes high, it forces the buffer to re-propagate the signals from input to output, from the top of the buffer to the bottom of the buffer. For example, given the following signal names: <i1> = SIG1 <i2> = SIG2 <i3> = SIG3 <o1> = SIG1-O <o2> = SIG2-O <o3> = SIG3-O On the rising edge of <enable>, first SIG1-O takes on the state of SIG1. Then, SIG2-O takes on the state of SIG2. Finally, SIG3-O takes on the state of SIG3. High/1 (level sensitive) = Enable buffer; Low/0 = Disable buffer |
|
Digital inputs: <i1> through <i4000> |
The digital state that is propagated to the corresponding output when <enable> is high. Every input has a corresponding output; each input/output pair is independent of other input/output pairs. For this reason the Buffer symbol is sometimes referred to as a compound AND symbol, where each input is AND-ed with <enable> to determine the state of its corresponding output. High/1 (level sensitive) = Propagate HIGH state to output; Low/0 = Propagate LOW state to output |
|
Digital outputs: <o1> through <o4000> |
Indicates the state of the corresponding input when <enable> is high. Although a digital signal normally can have only one driving source, the outputs of a Buffer symbol can legally be jammed with the outputs of other Buffer symbols, or with system inputs such as button presses. (The outputs of the Buffer symbol should not be tied to the outputs of any other logic symbol, however.) Jamming the outputs of Buffers allows a single Buffer output to trigger multiple events, or multiple Buffers to control different devices with one shared set of buttons. In these applications an Interlock symbol usually feeds the <enable> inputs of the Buffers. The break before make property of the Interlock ensures that only one Buffer will be enabled at one time. NOTE: Do not use multiple outputs with the same signal names, as this can lead to unexpected results. For example, given the following signal names: <i1> = SIG1 <i2> = SIG2 <i3> = SIG3 <o1> = OUTPUT <o2> = OUTPUT <o3> = OUTPUT <o4> = OUTPUT Initial States: <enable> = 0 SIG1 = 0 SIG2 = 1 SIG3 = 0 SIG4 = 0 OUTPUT = 0 When <enable> goes high, OUTPUT stays at 0. This is because of the top-down behavior of the propagation. The steps are:
The net result is that after the logic wave this buffer is in, there is no change in OUTPUT. High/1 = Input is HIGH; Low/0 = Input is LOW |
See also AND, Analog Buffer, Serial Buffer, Analog Scaling Buffer, Analog Scaling Buffer about 50%, Transition Gate